/****************************************************************************
 *  _____       ______  _____
 * |_   _|     |  ____|/ ____|
 *   | |  _ __ | |__  | (___    Institute of Embedded Systems
 *   | | | '_ \|  __|  \___ \   Zürcher Hochschule für Angewandte
 *  _| |_| | | | |____ ____) |  Wissenschaften
 * |_____|_| |_|______|_____/   8401 Winterthur, Switzerland
 *
 ****************************************************************************
 *
 * @version $Rev: 431 $
 * @author  $Author: mcrescenti $
 * @date    $Date: 2014-06-16 15:46:42 +0200 (lun., 16 juin 2014) $
 *
 ***************************************************************************/

#ifndef __PPS_PLL_HAL_H__
#define __PPS_PLL_HAL_H__

#include <stdint.h>
#include <stdbool.h>


//#include "packet/raw_packet.h"

#include "hal/register.h"


#define     RSYNC       (0x00000040)


typedef struct {
    union {
        uint32_t raw;
        struct {
            uint32_t    updated : 1;
            uint32_t    overflow : 1;
            uint32_t    limit_reached : 1;
            uint32_t    reserved : 1;
            uint32_t    periods : 28;
        } reg_t;
    };

} host_pll_pps_status_t;


typedef struct {
    union {
        uint32_t raw;
        struct {
            uint32_t    chkx : 1;           // filter set selector
            uint32_t    usdef : 1;          // use PPS default period
            uint32_t    enreg : 1;          // regulator enable
            uint32_t    antwu : 1;          // anti wind up protection
            uint32_t    res : 1;            // reserved
            uint32_t    ldacc : 1;          // load the accumulator value of the regulator
            uint32_t    rsync : 1;          // resync PPS out on PPS ref
            uint32_t    rstpp : 1;          // reset of PLL PPS block. Squelch PPS out
            uint32_t    reserved : 24;      // reserved
        } reg_t;
    };

} host_pll_pps_ctrl_t;

extern void pps_pll_hal_init        (uint32_t pps_pll);
extern void pps_pll_phase_get       (int32_t *phase);
extern void pps_pll_period_get      (uint32_t *correction);
extern void pps_pll_limits_get      (uint32_t *lim_tmax, uint32_t *lim_tmin);
extern void pps_pll_filter_get      (float *ki, float *kp, uint8_t filter_num);
extern void pps_pll_accumulator_get (uint32_t *accu);
extern void pps_pll_resync          (void);
extern void pps_pll_status_reg_get  (host_pll_pps_status_t *reg);
extern void pps_pll_ctrl_reg_get(host_pll_pps_ctrl_t *reg);

// simulation
extern void pps_pll_status_reg_set  (uint32_t value);
extern void pps_pll_control_reg_set  (uint32_t value);
extern void pps_pll_phase_set		(int32_t value);

#endif // __PPS_PLL_HAL_H__

